In recent years, the development of a through-electrode substrate arranged with a conducting part which conducts the front and rear surfaces of a substrate as an interposer between LSI chips is progressing. A through-electrode is formed in such a through-electrode substrate by filling a conductive material into a through-hole by electrolytic plating. As a conventional technology of a through-electrode substrate, a through-electrode substrate manufactured using a SOI wafer for example is disclosed (see Japanese Laid Open Patent Publication No. 2005-38942). This through-electrode substrate is arranged with a blind via hole having a depth which reaches a buried insulation layer in a support substrate layer of a SOI wafer, and a through-electrode is arranged by forming an inner wall insulation layer on an inner wall of the blind via hole. In addition, a contact hole is arranged in a section corresponding to a through-electrode in a buried insulation layer exposed by removal of a silicon layer.